The invention relates to a semiconductor device with a semiconductor body which is provided at a surface with a non-volatile electrically erasable memory comprising a number of memory elements with source and drain zones situated in a p-type surface region of the semiconductor body, adjoining the surface, and mutually separated by an interposed channel region, with a floating gate situated above the channel region and insulated therefrom by an interposed gate dielectric, and with a control gate insulated from the floating gate, information being written and erased through injection of hot electrons and hot holes into the floating gate, while the hot electrons are generated in the channel adjacent the drain zone through induction of a channel current between the source zone and drain zone. The invention also relates to a method of manufacturing this semiconductor device.
Such a device is known, for example, from European Patent Application EP-A 0 218 342, publication date 15.04.87.
Non-volatile memories with floating gates are known in the literature, for example, under the abbreviations EPROM and EEPROM (Electrically Erasable Programmable Read-Only Memory). An embodiment which is particularly popular at the moment is known under the name Flash-EEPROM or Flash-EPROM, with which a very high density can be obtained because each memory cell is formed by a single floating-gate transistor. The selection transistors, which are necessary for each memory element in an EEPROM of a usual type, are absent in the memory.
In the known device mentioned above, the transistor selected for writing is brought into the "ON state" by means of a high voltage applied to the control gate and the drain zone. Owing to the strong electric field near the drain zone, high-energy (hot) electrons are formed in the channel current with sufficient energy for flowing across the potential barrier of the gate dielectric to the floating gate, partly also under the influence of the electric field in the gate dielectric. Erasing of the information takes place in the known device through injection of hot holes which compensate the charge injected during writing.
This method differs from the usual method of erasing whereby electrons tunnel from the floating gate to a zone in the semiconductor body, for example, the source zone. A very thin dielectric is necessary in view of the tunnelling effect, which implies an added complication for the manufacturing process of the device, especially when the memory is embedded in a signal-processing IC, for example, a microcontroller which is manufactured by a different process. Such a thin tunnel oxide is unnecessary when erasion takes place with hot holes. The hot holes are formed by a "snap-back" method in which a comparatively high voltage is applied between the source zone (earth) and the drain zone (7 V), while the transistor is in the "OFF state". The control gate is then brought to a high voltage (13 V) for a short period whereby the transistor enters the "ON state", after which the voltage at the control gate is reduced to 0 V. Since the pn junction of the source zone remains forward-biased, an electron current is injected into the substrate so that a comparatively high drain current is maintained owing to lateral npn operation in spite of the low voltage at the control gate. Thanks to the low voltage at the control gate, hot holes formed by the strong field can be injected into the floating gate.
A disadvantage of the known device is that the "snap-back" mechanism described here is highly critical. Thus, the optimum voltage at the drain zone, which must be sufficient for obtaining the snap-back effect but must be lower than the breakdown voltage between the source and drain zone (punch-through voltage), strongly depends on doping concentrations and dimensions. Owing to the spread in such parameters, it is often difficult in practice to choose for the device such an adjustment that all cells can be erased in the manner described above.
During writing, a high voltage is applied to the selected word line in order to render the transistor in the selected cell conducting. Owing to capacitive coupling, the floating gates of the other cells connected to this word line may get a higher potential. It is possible then for electrons to flow towards the floating gates of these quasi-selected cells owing to the tunnelling effect. This phenomenon, which is known as "gate disturb", was described inter alia in the publication "Degradations due to hole trapping in flash memory cells" by Haddad et al. in IEEE Electron Device Letters, vol. 10, no. 3 March 1989, pp. 117-119. As is indicated in this publication, the "gate disturb" effect is reinforced by holes which are trapped in the gate dielectric. In a selected cell, moreover, it is found that writing becomes more difficult after a number of write/erase cycles in the sense that the difference between the threshold voltage in the programmed state and the threshold voltage in the non-programmed state becomes smaller. A possible explanation for this is that the electric field in the channel is weakened by the trapped holes in the gate oxide. Since the tunnelling effect is also strongly influenced by the electric field across the gate oxide, it is important to keep the programming voltage as low as possible, especially in memories in which erasing takes place with hot holes. Moreover, high voltages in general impose additional requirements, for example, on the dielectric insulation, parasitic channel formation, etc, which seriously hamper the embedding of the memory in an integrated circuit manufactured by a standard CMOS logic process. This also renders it desirable to keep the programming voltages and erasing voltages as low as possible.